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Raja Paul Perinbam, J.
- Reconfigurable Architecture for High Performance Turbo Decoder
Abstract Views :200 |
PDF Views:1
Authors
Affiliations
1 Electronics and Communication Department, R.M.D Engineering College, Chennai–601206, IN
2 Electronics and Communication Department, Professor , R.M.K Engineering College, Chennai – 601206, IN
3 Information and Technology Department, Professor & Head, R.M.D Engineering College, Chennai–601206, IN
1 Electronics and Communication Department, R.M.D Engineering College, Chennai–601206, IN
2 Electronics and Communication Department, Professor , R.M.K Engineering College, Chennai – 601206, IN
3 Information and Technology Department, Professor & Head, R.M.D Engineering College, Chennai–601206, IN
Source
Programmable Device Circuits and Systems, Vol 2, No 11 (2010), Pagination: 171-179Abstract
This paper presents a reconfigurable architecture for high performance turbo decoder based on Max Log Maximum a Posteriori (ML-MAP) algorithm using sliding window technique. The proposed architecture is based on standardizing the branch metric values to improve the speed of operation of the decoder and also configured to support three different constraint lengths. The intended reconfigurable decoder architecture has been implemented using Verilog HDL at RTL level and synthesized to investigate its performance in terms of area usage and timing delay. The proposed technique increases the throughput rate with marginal increase in area compared to the non reconfigurable decoder.Keywords
APP, LLR, ML-MAP, Reconfigurable, SISO.- Human Identification by Iris Recognition using Artificial Bee Colony Algorithm
Abstract Views :143 |
PDF Views:3
Authors
Affiliations
1 Dept of ECE, RMK Engineering College, IN
2 Dept of ECE, Karpaga Vinayaga College of Engineering and Technology, Chennai, IN
1 Dept of ECE, RMK Engineering College, IN
2 Dept of ECE, Karpaga Vinayaga College of Engineering and Technology, Chennai, IN